1. Field of the Invention
This invention relates to a process and apparatus for etching metal useful in the formation of integrated circuit structures. More particularly, this invention relates to a process and apparatus for etching metal portions of integrated circuit structure which exhibits high selectivity to photoresist mask material while also exhibiting good removal of metal etch residues.
2. Description of the Related Art
In the construction of integrated circuit structures, one or more metal interconnect layers are used to electrically connect together individual semiconductor devices formed on a substrate to thereby form desired electronic circuits. Conventionally such metal interconnects are constructed by first depositing a metal layer over the structure and then patterning the metal layer by forming a photoresist mask over the metal layer and then etching the exposed portions of the metal layer. The metal layer usually comprises aluminum and a low pressure plasma etch, using chlorine-based chemistry, is generally used to etch the aluminum metal. However, the aluminum metal used to form such aluminum metal interconnects typically comprises an alloy of aluminum and another metal, e.g., copper, in minor amounts, i.e., 10 wt. % or less, and may also contain small amounts of impurities. Such alloying materials and impurities can produce etch residues during the patterning of the metal layer, which residues must also be removed from the surface of the integrated circuit structure.
The successful removal of such residues has, in the past, required the use of high energy ion bombardment which is obtained by applying a high bias power to the substrate support on which the substrate rests during the etching process. By high power is meant a bias power equivalent to a bias power of at least 200 watts when a metal layer on a six inch diameter silicon substrate is being etched, with such equivalent power levels sometimes reaching as high as 1000 watts. While the use of such high bias power will result in successful removal of etch residues generated during the patterning of the metal layer, such a solution, in turn, generates a further problem: erosion of the photoresist mask. Erosion of the photoresist etch mask, in turn, can result in too much of the metal being etched away, resulting in an undesirable thinning and/or undercutting of the metal lines, or in extreme cases, complete etching away of the metal lines, resulting in an open circuit in the wiring structure being created. Such erosion of the photoresist mask can begin to occur when an equivalent bias power of greater than about 100 watts is used, and this erosion reaches an unsatisfactory level when equivalent bias power levels as high as 200 watts are utilized.
It would, therefore, be desirable to have a process and apparatus for the patterning of a metal layer in the construction of an integrated circuit structure wherein etch residues formed during the etching of the metal layer would be removed during the patterning process while still inhibiting or eliminating erosion of the photoresist mask.